Cadence Design Systems Assigned Patent for Method and Mechanism for Implementing Extraction for an Integrated Circuit Design
(Targeted News Service Via Acquire Media NewsEdge) By Targeted News Service
ALEXANDRIA, Va., Nov. 21 -- Cadence Design Systems, San Jose, Calif., has been assigned a patent (8,316,331) developed by four co-inventors for a "method and mechanism for implementing extraction for an integrated circuit design." The co-inventors are Eric Nequist, Monte Sereno, Calif., Richard Brashears, San Jose, Calif., Matthew A. Liberty, Lake Oswego, Ore., and Michael McSherry C. McSherry, Portland, Ore.
The abstract of the patent published by the U.S. Patent and Trademark Office states: "An improved method and system for stitching one or more islands of an integrated circuit design is disclosed. Multiple connected island objects in the IC design are first identified. At least one of the multiple identified connected island objects is then modified to form a modified island object. The modified island object may then be stitched into the multiple identified connected island objects. In some embodiments, stitching a modified island object may be implemented by tracking the endpoint(s), port(s), or node(s) of the connected island object being modified and stitched."
The patent application was filed on Jan. 7, 2011 (12/987,072). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,316,331&OS=8,316,331&RS=8,316,331
Written by Satyaban Rath; edited by Hemanta Panigrahi.
(c) 2012 Targeted News Service
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